The present invention relates generally to integrated circuit (IC) fabrication processes and, more particularly, to a high dielectric constant gate insulation film, and a deposition method for such film.
Current Si VLSI technology uses SiO.sub.2, or nitrogen containing SiO.sub.2, as the gate dielectric in MOS devices. As device dimensions continue to scale down, the thickness of the SiO.sub.2 layer must also decrease to maintain the same capacitance between the gate and channel regions. Thicknesses of less than 2 nanometers (nm) are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO.sub.2 requires that alternate materials be considered. Materials with high dielectric constants would permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. These so-called high-k dielectric films are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 4, while high-k films have a dielectric constant of greater than approximately 10. Current high-k candidate materials include titanium oxide (TiO.sub.2), zirconium oxide (ZrO.sub.2), tantalum oxide (Ta.sub.2 O.sub.5), and barium and strontium titanium oxide (Ba,Sr)TiO.sub.3. One common problem associated with the above-mentioned high-k dielectrics is that they develop a crystalline structure under
normal preparation conditions. As a result, the surface of the film is very rough. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Because of high direct tunneling currents, SiO.sub.2 films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts in the search for the replacement of SiO.sub.2, with TiO.sub.2 and Ta.sub.2 O.sub.5 attracting the greatest attention. However, high temperature post deposition annealing, and the formation of an interfacial SiO.sub.2 layer, make achieving equivalent SiO.sub.2 thicknesses (EOT) of less than 1.5 nm very difficult.
It would be advantageous if a high-k dielectric film could be used as an insulating barrier between a gate electrode and the underlying channel region in a MOS transistor.
It would be advantageous if improved high-k dielectric materials could be formed by simply doping, or otherwise adding additional elements to currently existing high-k dielectric materials.
It would be advantageous if the electrical properties, including electron affinity, of the high-k dielectric materials could be modified by simply doping, or otherwise adding additional elements to currently existing high-k dielectric materials.